Single electron MOSFET memory device and method

ABSTRACT

A memory device and related methods are described. The memory device includes a plurality of cells, each cell including a MOSFET having a source coupled to a first end of a channel, a drain coupled to a second end of the channel, a gate formed on a gate insulator and extending from the source to the drain and a plurality of conductive islands, each surrounded by an insulator, formed in the channel. The islands have a maximum dimension of three nanometers. The surrounding insulator has a thickness of between five and twenty nanometers. Each island and surrounding insulator is formed in a pore extending into the channel. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No. 09/140,624, filed Aug. 26, 1998 U.S. Pat. No. 6,125,062.

TECHNICAL FIELD

This invention relates to integrated circuit memory devices, and, more particularly, to a method and apparatus for providing high density, high storage capacity, low power, nonvolatile memory devices.

BACKGROUND OF THE INVENTION

Single electron devices, and particularly single electron memory cells, are presently of great interest, due to potential advantages in memory cell size and power dissipation, compared to memory technologies currently in use. As used herein, the term “single electron device” refers to an electronic device capable of providing a repeatable and measurable response to the presence or absence of a single electron.

As device sizes have shrunk over the last several decades, the number of electrons contributing to the drain current in field effect transistors (“FETs”) used in memory devices has correspondingly decreased. Extrapolation from these trends suggests that in another decade, FETs will have drain currents including as few as ten electrons at a time. When so few electrons contribute to a current and therefore to a signal, normal fluctuations in the number of electrons present in a volume of semiconductor material can lead to uncertainty or error in the signal that the current represents.

Memories using single electron memory cells provide certainty in numbers of electrons representing data in a memory cell and therefore help to avoid problems due to fluctuations in the number of electrons that are present in a transistor at one time. Memory cells employing single electron transistors are also extremely simple and can be quite small. For example, a memory structure employing vertically stacked cells to provide an area per bit of 0.145 micrometers squared is described in “A 3-D Single-Electron-Memory Cell Structure with 2F² per bit” by T. Ishii et al. (IEDM 97), pp. 924-926.

The combination of size, power requirements and simplicity make single electron structures promising candidates for very high capacity memory integrated circuits. This is discussed in more detail in “Single-Electron-Memory Integrated Circuit for Giga-to-Tera Bit Storage” by K. Yano et al., 1996 Intl. Solid State Circuits Conf. (Feb. 9, 1996), pp. 266-267 and “A 128 Mb Early Prototype for Gigascale Single-Electron Memories” by K. Yano et al., 1998 Intl. Solid State Circuits Conf. (Feb. 7, 1998), pp. 344-345.

FIG. 1A is a simplified schematic diagram of a typical two-terminal single electron device 20, in accordance with the prior art. The single electron device 20 includes first 22 and second 24 electrodes and an island 26 formed from conductive material, which may be semiconductor material, as discussed in U.S. Pat. No. 5,731,598, entitled “Sincle Electron Tunnel Device And Method For Fabricating The Same” issued to H. Kado et al. (Mar. 24, 1998). The first 22 and second 24 electrodes are each separated from the island 26 by small insulating gaps 28, 28′. The first 22 and second 24 electrodes, the island 26 and the gaps 28, 28′ are all collectively mounted on an insulating substrate 30 or are surrounded by an insulator. The gaps 28, 28′ may be formed of any insulating material but must be small enough to allow conduction band electrons 32 (hereinafter “electrons”) to tunnel through them in response to a voltage V coupled across the first 22 and second 24 electrodes. The voltage V is provided by an external source. represented in FIG. 1A by a battery 34.

A first condition for trapping one or more electrons 32 on the island 26 is that the resistance R between the island 26 and other structures on the substrate 30 must be greater than a quantum resistance R_(k), as is discussed, for example, in “Single-electron devices” by H. Ahmed et al. Microelectronic Engineering 32 (1996), pp. 297-315, and “Single electron electronics: Challenge for nanofabrication” by H. Ahmed, J. Vac. Sci. Technol. B 15(6) (Nov./Dec. 1997), pp. 2101-2108. When the first 22 and second 24 electrodes and the island 26 are mounted on the insulating substrate 30 and are surrounded by an insulator such as air. the primary resistance R between the island 26 and any other structure is set by tunneling resistances R_(t) associated with the gaps 28, 28′ separating the island 26 from the first 22 and second 24 electrodes. The quantum resistance R_(k) equals h/q², or about 26 kΩ, where h is Planck's constant and q represents the charge of a single electron. This first condition will be satisfied for all of the examples considered herein but is included for completeness sake.

A second condition is that allowed states for these electrons 32 must be separated from a conduction band edge E_(C) by an “electron charging energy” that is given as q²/2C, where C represents a capacitance of the island 26. In other words, a first electron 32 that is introduced onto the island 26 will occupy an allowed state having a potential energy that is greater than that of the conduction band edge E_(C) for the material forming the island 26 by q²/2C.

A third condition is that, for the electron or electrons 32 to be trapped on the island 26, the electron charging energy q²/2C must be substantially greater than an average thermal energy kT, or q²/2C>kT, where k represents Boltzmann's constant and T represents temperature in Kelvin. The capacitance C must be on the order of one attoFarad for electrons 32 to be trapped on the island 26 for any appreciable length of time at room temperature (kT=0.026 eV at room temperature). For example, an island 26 having a capacitance of 10⁻¹⁶ F is about 100 nanometers in diameter but can only exhibit single-electron effects at temperatures at or below about 4 Kelvin. Islands 26 having diameters of one to five nanometers exhibit significant single-electron effects at room temperature (circa 300 K).

FIG. 1B is a simplified potential energy diagram for the device 20 of FIG. 1A showing a potential well 40, in accordance with the prior art. FIG. 1B shows Fermi levels (“E_(F)”) 42, 44 in the first 22 and second 24 electrodes, respectively, a lowest allowed state 46 for one electron 32 in the potential well 40 on the island 26, and eneray barriers 48, 48′ associated with insulating materials forming the gaps 28, 28′, respectively. An important property of the device 20 of FIG. 1A is that no significant current can flow through the device 20 until a magnitude of the potential V due to the external source 34 equals or exceeds the electron charging energy or V≧q²/2C. FIG. 1C is a simplified potential energy diagram illustrating the potential V setting the Fermi level 42 at the left side of the Figure equal to the lowest allowed state of the potential well 40, i.e., at the onset of conduction, in accordance with the prior art.

FIG. 1D is a simplified graph of an I-V characteristic 50 for the device 20 of FIG. 1A, in accordance with the prior art. The I-V characteristic 50 shows essentially no conduction until the applied voltage V reaches a threshold V_(C), causing the Fermi level 42 on the electron supply side to be equal to the electron charging energy q²/2C. The region of essentially no conduction is known as the Coulomb blockade region. When the applied voltage V reaches the threshold V_(C), known as the Coulomb gap voltage. the energy barrier effectively vanishes. Linear I-V dependence is seen in FIG. 1D for voltages having an absolute magnitude exceeding V_(C).

FIG. 2 is a simplified schematic illustration of a typical field effect transistor (“FET”) 60 that includes the island 26 of FIG. 1A for storing one or more electrons 32, in accordance with the prior art. The FET 60 includes all of the elements of the two-terminal device 20 of FIG. 1 and additionally includes a gate 62 having a capacitance C_(G) and a gate bias supply 64. The gate bias supply 64 includes a first electrode coupled to the gate 62 and a second electrode coupled to one side of the supply 34 providing the voltage V. The FET 60 has a channel 66 formed from semiconductor material that is coupled to the first 22 and second 24 electrodes.

Several examples of FETs 60 capable of providing repeatable output signals indicative of single electron 32 storage on the islands 26 are described in “A Room-Temperature Silicon Single-Electron Metal-Oxide-Semiconductor Memory With Nanoscale Floating-Gate and Ultranarrow Channel” by L. Guo et al., Appl. Phys. Lett. 70(7) (Feb. 17, 1997), pp. 850-852 and “Fabrication And Characterization of Room Temperature Silicon Single Electron Memory” by L. Guo et al., J. Vac. Sci. Technol. B 15(6) (November/December 1997), pp. 2840-2843. Similar FETs 60 are described in “Room Temperature Operation of Si Single-Electron-Memory with Self-Aligned Floating Dot Gate” (IEDM 1996), pp. 952-954; Appl. Phys. Lett. 70(13) (Mar. 31, 1997), pp. 1742-1744 and “Si Single Electron Tunneling Transistor With Nanoscale Floating Dot Stacked on a Coulomb Island by Self-Aligned Process”, Appl. Phys. Lett. 71(3) (Jul. 21, 1997), pp. 353-355, all by A. Nakajima et al. These FETs 60 employ feature sizes as small as 30 nanometers and require much closer alignment between elements than 30 nanometers. Formation of such small feature sizes using electron beam lithography does not presently lend itself to mass production.

These FETs 60 employ a floating island 26 between the gate 62 and the channel 66 to modulate conductivity in the channel 66. In these FETs 60, the island 26 spans the width of the channel 66.

It will be appreciated that other techniques for forming the islands 26 may be emploved. For example, shallow implantation of relatively high doses (e.g., ca. 5-50×10¹⁴/cm²) of silicon or germanium at relatively low energies (e.g., ca. 20 keV) into relatively thin (e.g., ca. 5-20 or more nanometers) silicon dioxide layers, followed by annealing, provides islands 26 formed from nanocrystals of the implanted species that are insulated from each other and from an underlying silicon region, as described in “Fast and Long Retention-Time Nano-Crystal Memory” by H. Hanafi et al., IEEE Trans. El. Dev., Vol. 43, No. 9 (Sep. 1996), pp. 1553-1558. Performance of memories using islands 26 formed from nanocrvstals in proximity to the channel 66 is discussed in “Single Charge and Confinement Effects in Nano-Crystal Memories” by S. Tiwari et al., Appl. Phys. Lett. 69(9) (Aug. 26, 1996), pp. 1232-1234.

Prior art FETs may provide multiple islands 26 between the gate 62 and the channel 66. and are capable of storing multiple electrons 32. As a result these FETs are analogous to conventional flash memories and are capable of multilevel signal storage and readout. An example of an arrangement for discriminating between multiple signal levels that may represent a stored signal is given in “Novel Level-Identifying Circuit for Multilevel Memories” by D. Montanari et al., IEEE Jour. Sol. St. Cir., Vol. 33, No. 7 (July 1998), pp. 1090-1095.

FETs 60 including one or more islands 26 suitable for capture of electrons 32 thus are able to provide measurable and repeatable changes in their electrical properties in response to capture of the electron or electrons 32 on at least one island 26. Moreover, these FETs 60 provide these changes in a convergent manner, i.e., the changes may be produced by storage of a single electron 32, and storage of that single electron 32 can inhibit storage of another electron 32. In this way, some of the FETs 60 avoid some problems due to number fluctuations in the population of electrons 32 that could otherwise be troublesome for FETs 60 having very small populations of electrons 32.

Additionally, the energy barriers 48, 48′ cause the single electron device 20 and the FETs 60 to store trapped electrons 32 for significant periods of time, even in the absence of externally applied electrical power (e.g., voltage sources 34, 64). As a result, a nonvolatile memory function is provided by these devices 20 and FETs 60.

While single electron devices 20 and FETs 60 show great promise as memory cells for very high density memory arrays, fabrication difficulties prevent mass production of memory arrays using these devices 20, 60 as memory cells. Difficulties in regulating the size of the island or islands 26 and the thickness of the surrounding dielectric materials forming the gaps 28, 28′ cause problems, particularly with respect to uniformity of device characteristics across many similar devices on a wafer or substrate. Difficulties in realizing the fine line interconnections (e.g., ca. 0.4 micron pitch) and other needed elements also cause poor yields in fabrication of these devices 20, 60.

There is therefore a need for a method for fabricating single electron devices that is robust and that provides reproducible single-electron device characteristics.

SUMMARY OF THE INVENTION

In one aspect, the present invention includes a memory cell including a MOSFET having a source coupled to a first end of a channel of semiconductor material, a drain coupled to a second end of the channel, a gate formed on a gate insulator on the channel and extending from the source to the drain and a plurality of islands of conductive material having a maximum dimension of three nanometers and surrounded by an insulator having a thickness of between five and twenty nanometers. Each island and surrounding insulator is formed in a pore extending into the channel. As a result, electrons may tunnel into or out of the islands with the assistance of electrical fields resulting from signals coupled to the gate, source and drain. The capacitance of the islands is small enough that single electrons stored on the islands provide externally observable changes in the memory cells.

In other aspects, the present invention provides methods for reading data from, writing data to and erasing memory cells capable of storing data by the presence or absence of a single electron in an island of conductive material contained in the memory cells. The reading, writing and erasing operations may be accompanied by a verification process that compensates for stored charge. trap generation and the like that otherwise might obscure desired data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a simplified schematic diagram of a typical two-terminal single electron device, in accordance with the prior art.

FIG. 1B is a simplified potential energy diagram for the device of FIG. 1A, in accordance with the prior art.

FIG. 1C is a simplified potential energy diagram, illustrating the potential V settina the Fermi level at the left side of the Figure equal to the lowest allowed state of the potential well of FIG. 1B, in accordance with the prior art.

FIG. 1D is a simplified graph of an I-V characteristic for the device of FIG. 1A, in accordance with the prior art.

FIG. 2 is a simplified schematic illustration of a typical field effect transistor that includes the island of FIG. 1A for storing one or more electrons, in accordance with the prior art.

FIG. 3A is a simplified plan view of a memory device including memory cells employing single electron memory devices having electrical characteristics similar to those of the devices of FIGS. 1 and 2, in accordance with embodiments of the present invention.

FIG. 3B is a simplified isometric view of a single electron MOSFET memory device in the memory cell of FIG. 3A, in accordance with embodiments of the present invention.

FIG. 3C is a simplified cross-sectional view of the device of FIG. 3B, showing islands included within the semiconductor material of the body, in accordance with embodiments of the present invention.

FIG. 4 is a simplified flow chart of a process for reading the memory cell of FIGS. 3A-C, in accordance with embodiments of the present invention.

FIGS. 5 and 6 are simplified flow charts for processes for writing data to the memory cell of FIGS. 3A-C and for erasing data stored in the memory cell, respectively. in accordance with embodiments of the present invention.

FIG. 7 is a graph representing storage and erase time estimates for various energy barriers. in accordance with embodiments of the present invention.

FIG. 8 is a simplified flowchart of a process for forming the islands of FIGS. 1 and 2, in accordance with embodiments of the present invention.

FIGS. 9A and 9B are simplified cross-sectional views of the islands as they are being formed using the process of FIG. 8, in accordance with embodiments of the present invention.

FIG. 10 is a simplified block diagram of a computer system including the memory device of FIGS. 3A-C, in accordance with embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3A is a simplified plan view of a memory device 72 including a memory cell 73 having electrical characteristics similar to those of the devices 20 and 60 of FIGS. 1 and 2, in accordance with embodiments of the present invention. The memory device 72 includes a column addressing circuit 74 coupled to a plurality of column address lines 75, and a row addressing circuit 76 coupled to a plurality of row address lines 77. The memory cell 73 is located at an intersection of a column address line 75 and a row address line 77 and is addressed by activation of the column 75 and row 77 address lines coupled to the memory cell 73, as is discussed below in more detail.

FIG. 3B is a simplified isometric view of a single electron MOSFET memory device 80 in the memory cell 73 of FIG. 3A, in accordance with embodiments of the present invention. The MOSFET 80 includes a body 82 having first 84 and second 86 electrodes formed at opposing ends. In one embodiment, the first 84 and second 86 electrodes form low resistance contacts to the body 82. The first electrode 84 is coupled to a row address line 77 and acts as a drain for the MOSFET 80. The second electrode 86 is coupled to a column address line 75 and acts as a source for the MOSFET 80. In one embodiment, the body 82 includes p-type semiconductor material havina an acceptor concentration of about 10¹⁵/cm³ or less and the first 84 and second 86 electrodes are N+ contacts to the body 82.

The MOSFET 80 includes a gate 88 coupled to a gate address line 90 for storing data in, and erasing data stored in, the MOSFET 80, and for regulating current through-the MOSFET 80. The MOSFET 80 also optionally includes a backgate 88′ coupled to a backgate address line 90′ for regulating current through the MOSFET 80, and for optionally assisting in data storage and erasure. In one embodiment, the gate 88 and backgate 88′ are formed from polysilicon using conventional processing techniques.

FIG. 3C is a simplified cross-sectional view of the MOSFET 80 of FIG. 3B, showing islands 26 (see FIGS. 1 and 2) included within semiconductor material 98 forming the body 82 of the MOSFET 80, in accordance with embodiments of the present invention. Each island 26 is surrounded by a dielectric 100 that provides the energy barriers 48, 48′ (FIGS. 1B and C) associated with the gaps 28, 28′, which insulate the island 26 from other islands 26 and from the semiconductor material 98. The gate 88 is biased to be more positive than the second electrode 86, creating a channel 99 extending from the second electrode 86 to the first electrode 84.

The MOSFET 80 of FIGS. 3A-C has a first state exhibiting a first current-voltage characteristic when no electrons 32 are stored on the islands 26 within the MOSFET 80. The MOSFET 80 has a second state exhibiting a second current-voltage characteristic when one or more electrons 32 are stored in one or more islands 26 contained in the body 82 of the MOSFET 80. In the second state, less current passes between the first electrode 84 and the second 86 electrode for a given voltage difference between the first 84 and second 86 electrodes than in the first state, and this difference may be detected by sensing circuitry (not illustrated) coupled to the column 75 or the row 77 address lines. Processes for switching the MOSFET 80 between the first and second states by storage and removal of electrons 32 from the island or islands 26 in the body 82 of the MOSFET 80 are explained in more detail below.

To store one or more electrons 32 in the body 82 of the MOSFET 80, the column address line 75 is coupled to a first voltage (e.g., ground) and the row address line 77 is coupled to a second voltage (e.g. four volts) sufficient to cause single electrons 32 (FIG. 1) to tunnel into and to be stored on one or more of the islands 26 in the body 82 of the MOSFET 80, as is explained below in more detail with reference to FIG. 5. As a result, the MOSFET 80 changes from the first state to the second state.

To erase information represented by one or more stored electrons 32 stored on the island or islands 26 within the body 82 of the MOSFET 80, the row 77 or column 75 (or both) address line is coupled to an electron sink (e.g., ground). A negative potential is applied to the gate 88 sufficient to completely deplete the semiconductor material 98 forming the body 82 of mobile charge carriers (i.e., electrons 32 or holes) and to tilt the energy barriers 48, 48′ (FIG. 1) of the islands 26 to allow any stored electrons 32 to tunnel out of the island or islands 26. Electrons 32 tunneling out of the islands 26 are removed from the semiconductor material 98 by electrical fields induced by a negative voltage applied to the gate electrode 88. A positive voltage may be applied to the backgate electrode 88′ to aid erasure. As a result, the MOSFET 80 is restored to the first state.

A change in a current I_(DS) between the first 84 and the second 86 electrode, corresponding to a difference ΔI_(DS) in the current I_(DS) between the first and second states, can be estimated as follows. A total charge Q_(T) stored on the islands 26 divided by a gate capacitance C_(G) for the MOSFET 80 equals a change in threshold voltage ΔV_(T) for the MOSFET 80, or ΔV_(T)=Q_(T)/C_(G). For a MOSFET 80 having a gate insulator 10 nanometers thick. a gate length L of 10⁻⁴ cm and a gate width W of 10⁻⁴ cm, the gate capacitance C_(G) is about 3.3 femtoFarad. The change in threshold voltage corresponding to a single electron stored on one of the islands 26 is thus 0.05 millivolts. The drain-source current I_(DS) is given as I_(DS)=μC_(G)(W/L) (V_(GS)−V_(T))²/2, where V_(GS) represents the voltage between the gate 88 and the source 86 for the MOSFET 80 and μ represents the electron mobility. An estimate for a change in the drain-source current ΔI_(DS) due to a change in threshold voltage ΔV_(T) is ΔI_(DS)=μC_(G)(W/L)(V_(GS)−V_(T))ΔV_(T). For this example, a mobility μ of 600 cm²/(v-sec) and voltage difference (V_(GS)−V_(T)) of two volts corresponds to a decrease in current ΔI due to one stored electron 32 of 10 nanoamperes.

In one embodiment, the body 82 of the MOSFET 80 may have a length L of about one micrometer (10⁻ 4 cm), a cross-sectional area A of about 10⁻⁸ cm² and a thickness of the body 82 of about one micrometer. A free carrier concentration of 10¹⁵/cm³ or less allows the gate 88 and the backgate 88′ to be able to deplete the semiconductor material 98 with relatively low applied voltages.

FIG. 4 is a simplified flow chart of a process 120 for reading the memory cell 73 of FIG. 3A, in accordance with embodiments of the present invention. The process 120 begins in a step 122 by activating one of the column address lines 75 and one of the row address lines 77 of FIGS. 3A-C to address one of the memory cells 73, as is discussed below in more detail. In a step 124. a bias current I_(B) or voltage V_(B) is applied to the addressed memory cell 73. In a step 126, the addressed memory cell 73 is coupled to a sensing circuit (not shown). In some embodiments, a query task 128 then compares a measured response X_(M) to a threshold X_(T) to determine if a logical “1” or a logical “0” is stored in the memory cell 73 as is described below in more detail.

In one embodiment, when a bias current I_(B) is supplied from a current source (not shown) to, for example, the first electrode 84 of the addressed memory cell 73, the measured response X_(M) is a voltage, such as a drain-source voltage, measured across the first 84 and second 86 electrodes. When. for example, the query task 128 determines that the measured response X_(M) exceeds the threshold X_(T), at least one electron 32 is stored in the memory cell 73 and the memory cell 73 is storing a first logical state. When the querv task 128 determines that the measured response X_(M) does not exceed the threshold X_(T), no electron 32 is stored in the memory cell 73 and the memory cell 73 is storing a second logical state.

Conversely, in another embodiment, when a bias voltage V_(B) is supplied from a voltage source (not shown) to, for example, the gate 88 of the addressed memory cell 73, the measured response X_(M) is a current, such as a drain current, measured, for example, at the first electrode 84. When the query task 128 determines that the measured response X_(M) exceeds the threshold X_(T), no electron 32 is stored in the memory cell 73 and the memory cell 73 is in the second logical state. When the query task 128 determines that the measured response X_(M) does not exceed the threshold X_(T), at least one electron 32 is stored in the memory cell 73 and the memory cell 73 is in the first logical state.

When the query task 128 determines that the memory cell 73 is in the first logical state, the comparison circuit indicates that the memory cell 73 is in the first logical state, e.g., that a logical “1” is stored in the memory cell 73, in a step 130. When the query task 128 determines that the memory cell 73 is in the second logical state. the comparison circuit indicates that a logical “0” is stored in the memory cell 73 in a step 132. The process 120 ends following either step 130 or step 132.

In another embodiment, the query task 128 discriminates between a plurality of different logical values or states that may be stored in the memory cell 73 by comparing the measured response X_(M) to a plurality of thresholds X_(Ti). An example of an arrangement for discriminating between multiple signal levels that may represent a stored signal is given in “Novel Level-Identifying Circuit for Multilevel Memories” by D. Montanari et al., IEEE Jour. Sol. St. Cir., Vol. 33, No. 7 (July 1998), pp. 1090-1095. An example of a circuit and method for programming, reading and erasing multiple single electron differences in the FETs 80 of FIGS. 3A-C is given in “Multi-State Flash Memory Cell and Method for Programming Single Electron Differences” by L. Forbes, U.S. Pat. No. 5,740,104. After the querv task 128 determines the correct logical value for the data stored in the memory cell 73, the data comparison circuit indicates the correct logical value in the steps 130-132 and the process 120 ends.

FIGS. 5 and 6 are simplified flow charts for processes 140 and 160 for writing data to the memory cell 73 of FIG. 3A and for erasing data stored in the memory cell 73, respectively, in accordance with embodiments of the present invention. The processes 140 and 160 both use a verification process similar to a conventional verification process used with flash memories to compensate for variations in memory cell characteristics from one memory cell 73 to another, as is described in “Verify: Key to the Stable Single-Electron-Memory Operation” by T. Ishii et al. (1997 IEDM), pp. 171-174.

With reference now to FIG. 5, the write process 140 begins in a step 142 by activating one of the column address lines 75 and one of the row address lines 77 of FIGS. 3A-C to address one of the memory cells 73. In a step 144, a write pulse, which may be either a current I_(W) or a voltage V_(W) pulse, is applied to the addressed memory cell 73. In some embodiments, the step 144 is used to write a binary value to the memory cell 73. In other embodiments, the step 144 is used to write one of a plurality of possible values or data entries to the memory cell 73 by injecting a controlled number of electrons 32 into the islands 26 of the memory cell 73.

In a step 146, an index variable n, corresponding to a number of write cycles applied to this memory cell during this write process 140, is incremented. In a step 148, the memory cell 73 is read by sampling a voltage or current associated with the memory cell 73. A query task 150 then compares the read data to the data written to the memory cell 73 in the step 144.

When the query task 150 determines that the read data and the write data agree, the process 140 ends. When the query task 150 determines that the read data and the write data do not agree, control passes to a query task 152 to determine if a maximum number of cycles N has been reached (i.e., is n≧N?). The maximum number of cycles N is chosen to allow all working memory cells 73 to be programmed, despite differences in programming time between cells 73, without wasting excessive amounts of time in attempts to program defective memory cells 73. When the query task 152 determines that the maximum number of cycles N has not been reached, control passes to the step 144, and steps 144-150 or 152 repeat. When the query task 152 determines that the maximum number of cycles N has been reached, a step 154 records that a write failure has occurred and the process 140 ends.

In some embodiments, the record of a write failure that is generated in the step 154 may be used to construct a conventional memory map describing addresses of defective memory cells 73. Memory maps are used in order to avoid writing data to, or attempting to write data to, or reading data from, memory cells 73 that are defective. In some embodiments, the record of a write failure that is generated in the step 154 may be used to replace defective memory cells 73 with memory cells 73 that are known to be working properly, as is conventional in fabrication and repair of memory devices such as dynamic random access memories.

In the step 144, where a write pulse is applied to the memory cell 73, a finite number of electrons 32 are injected into the island or islands 26. A probability of write failure is finite and nonzero because injection of electrons 32 into the potential wells 40 (FIG. 1C) is essentially stochastic. For example, a failure probability of 0.1% is unacceptable in modern memory devices. Additionally, characteristics of the memory cell 73 may change with time, due to generation of new trapping centers or by trapping of charge in or near the memory cell 73.

Reading data from the memory cell 73 after a write pulse has been applied to the memorv cell allows determination that a write failure has occurred. By making the write pulses I_(W) or V_(W) longer as n increases, the probability of trapping the desired number of electrons 32 increases substantially and may approach unitv. In one embodiment, a width W_(W) of the write pulses I_(W) or V_(W) depends geometrically on n, e.g., W_(W)(n)∝2^(n), nε{I}. In another embodiment, the amplitude of the write pulses depends arithmetically on n. e.g, V_(W)(n)∝V_(W)(o)(1+n/M), nε{I}, where V_(W)(o) represents an initial value and M represents a proportionality constant.

With reference now to FIG. 6, the erase process 160 begins in a step 162 by activating one or more of the column address lines 75 and one or more of the row address lines 77 of FIGS. 3A-C to address one or more of the memory cells 73. In one embodiment, the step 162 selects a group of memory cells 73, which may be a subset of the memory cells on one memory device 72, may be all of the memory cells 73 on a memory device 72 or may include memory cells 73 from more than one memory device 72. In a step 164, an erase voltage pulse V_(E) is applied to the addressed memory cell 73. In one embodiment, the erase pulse includes a negative voltage pulse applied to the gate 88. A positive erase pulse may also be applied to the optional backgate 88′. In a step 166, an index variable n, corresponding to a number of erase cycles applied to this memory cell 80 during this erase process 160, is incremented. In a step 168, the memory cell 73 is read by sampling a voltage or current associated with the memory cell 73. A query task 170 then compares the read data to an expected value (e.g., corresponding to an absence of stored electrons 32) to determine if the contents of the memory cell 73 were erased in the step 164.

When the query task 170 determines that the contents of the memory cell 73 are erased, the process 160 ends. When the query task 170 determines that the contents of the memory cell 73 are not erased, control passes to a query task 172 to determine if a maximum number of cycles N has been reached (i.e., is n≧N?). As with the write process 140 of FIG. 5, N is chosen to balance differences in erase time from one memory cell 73 to another cell 73 without spending excessive time to erase defective memory cells 73. When the query task 172 determines that the maximum number of cycles N has not been reached. control passes back to the step 164, and steps 164-170 or 172 repeat. In accordance with embodiments of the invention, the erase pulses V_(E) may be varied with n as described above for the write pulses I_(W) or V_(W) in connection with the process 140 of FIG. 5. When the query task 172 determines that the maximum number of cycles N has been reached, a step 174 records that an erase failure has occurred The process then 160 ends.

In one embodiment, individual memory cells 73 are erased as needed for storage of new data. In another embodiment, all of the memory cells 73 in a group or in an entire memory device 72 are erased en masse, by addressing a group of memory cells 73 in the step 162 and application of the erase pulses in the step 164 to all of the memory cells 73 in. the group or in the memory device 72 simultaneously. The steps 166-174 are then carried out for each memory cell 73 individually, with a step of addressing the individual memory cells 73 being carried out prior to the step 166 of incrementing the index variable n. In another embodiment, the memory cells are erased en masse, however, the steps 166-174 are carried out as steps 146-154 of the verified write process 140 of FIG. 5.

An advantage of en masse erasure is that the erase process 160 is slow, typically requiring milliseconds. Erasure of the entire memory device 72 one memory cell 73 at a time takes much longer than erasure of the entire memory device 72 en masse, and this is more exaggerated as the number of memory cells 73 in the memory device 72 increases.

Several factors affect storage times τ_(S), also known as latency, for memory cells 73 incorporating islands 26 for storage of one or more electrons 32. In general, τ_(s)∝e^((ΔE/kT))e^((d/d) ^(_(o)) ⁾, where ΔE represents the energy level difference between the energy barriers 48, 48′ and the lowest allowed state in the island 26 and d/d_(o) represents a normalized thickness of the gaps 28, 28′. Larger ΔE values or large d/d_(o) values provide for longer storage times but also require higher write and erase pulse magnitudes and greater pulse durations. Additionally, ΔE is a function of the material forming the island 26 and the material forming the gaps 28, 28′. The energy level difference ΔE may be estimated by subtracting the electron affinity χ_(INS) for the material forming the gaps 28. 28′ from the electron affinity χ_(ISL) for the material making up the island 26 and then adding the electron charging energy q²/2C, i.e., ΔE=χ_(ISL)−χ_(INS)+q²/2C. Representative values for electron affinities χ for several materials are summarized below in Table I. Measured or achieved electron affinities χ depend strongly on surface treatment and surface contamination and may vary from the values given in Table I.

TABLE I Electron affinities χ for selected materials. χ (eV) Material Use 4.05 Si Islands 3.6/3.7* SiC Islands 1.4** C (diamond) Islands 0.9-4.05 Silicon oxycarbide (projected) Islands 0.9 SiO₂ Gaps *depending on surface treatment **diamond can manifest different values, including negative values.

FIG. 7 is a graph representing estimated storage 176 and erase 178 time estimates for various island electron affinities χ_(ISL) together with SiO₂ barriers in accordance with embodiments of the present invention. The left ordinates correspond to a logarithm of retention time 176 at constant temperature, while the right ordinates correspond to a logarithm of erase time 178 at constant erase voltage. Erase times 178 for the memory device 72 are determined in part by the height of the energy barrier 48, 48′ (FIGS. 1B and C) surrounding the island 26. Lower energy barriers 48, 48′ require lower voltage, shorter erase pulses because lower energy barriers 48, 48′ provide shorter tunneling distances and much higher tunneling probabilities. Short erase times 178 are desirable for some applications of electronically-erasable memories such as the memory device 72.

Lower barriers 48, 48′ also result in shorter retention times 176 due to thermal activation of electrons 32 over or through the energy barriers 48, 48′. The islands 26 may be formed from silicon, from microcrystalline diamond-like films of Si_((1−X))C_(X), with the composition ratio, x, ranging from 0.5 to one, or from silicon oxycarbide compounds, to provide electron affinities χ ranging between about 4.05 eV and 0.9 eV or less (see Table I), corresponding to energy barriers ΔE ranging from about 3.95 to about 0 eV (ignoring the charging voltage). By changing the composition of the islands 26 and the thickness of the surrounding insulator, and thus the height of the energy barriers 48, 48′, charge retention times 176 can be changed from seconds, characteristic of DRAMs, to years, characteristic of hard disk drives. As a result, the memory device 72 can either be made to emulate a DRAiM or a hard disk drive by varying the composition of the islands 26. One device type can then perform all memory functions. Moreover, becaus e retention characteristics of the memory devices may be adjusted by simply changing various process parameters or using different materials, memory devices having different charge retention characteristics may be fabricated onto the same device. For example, a single memory device may be fabricated to include both a memory array having memory devices with retention characteristics similar to conventional RAM memory cells and another memory array having memory devices with retention characteristics similar to a hard disk drive.

FIG. 7 illustrates that storage 176 and erase 178 times vary exponentially with the height of the energy barrier 48, 48′. Presently, memories using polycrystalline silicon floating gates embedded in silicon dioxide are estimated to have charge retention times 176 of millions of vears at 85° C. because the energy barriers 48, 48′ are larae (3.2 eV), resulting in erase times 178 in the millisecond range. The high electric fields required for erasure as a result of the large energy barriers 48, 48′ may result in reliability problems or, in the worst case, lead to breakdown and catastrophic failure of the device 72. An island 26 may be composed of a material of lower or adjusted barrier height, such as diamond-like compounds of silicon, carbon and oxygen, to provide desired energy barriers 48, 48′. As a result. an acceptable retention time 176 can be established, whether seconds or years, by varying the relative concentrations of Si, C and O, thereby varying the electron affinity χ for the islands 26. This then determines the height of the energy barriers 48, 48′ and therefore, in part, the erase time 178 for a particular erase voltage.

FIG. 7 shows the concepts involved using rough order-of-magnitude estimates of the variations of storage 176 and erasure 178 times with barrier height ΔE. The same device structure can be used either as replacements for DRAMS or as replacements for hard disk drives. Only the composition of the island 26 needs to be changed in order to change the retention time 176 and the erasure characteristics 178. This may be done on one integrated circuit so that radically different types of memory functions are realized on one integrated circuit.

FIG. 8 is a simplified flowchart of a process 180 for forming the islands 26 of FIGS. 1 and 2, and FIGS. 9A-9E are simplified cross-sectional views of the islands 26 as they are being formed using the process 180 of FIG. 8, in accordance with embodiments of the present invention. The process 180 (FIG. 8) begins in a step 182 with formation of voids or pores 202 (FIG. 9A) in a suitable silicon substrate or layer 98 (FIGS. 3C and 9A-9E). In one embodiment, the voids or pores 202 are formed by processes similar to those described in “On the Morphology of Porous Silicon Layers Obtained by Electrochemical Method” by G. Graciun et al., International Semiconductor Conference CAS '95 Proceedings (IEEE Catalog No. 95TH8071) (1995), pp. 331-334. In one embodiment, a current density of between 1.5 and 30 mA/cm² is employed together with either 36 weight % HF-ethanol 1:1 or 49 weight % HF-ethanol 1:3. Pores 202 are to have the desired characteristics readily and uniformly formed using simple and easily controlled processes.

In a step 184, the silicon 98 including interiors of the pores 202 is oxidized to provide a thin oxide layer 100 (FIG. 8). In one embodiment, the silicon 98 is oxidized to provide the oxide layer 100 to have a thickness of between 2.5 and ten nanometers. The step 184 may be carried out using conventional oxidation techniques. In one embodiment, an inductively-coupled oxygen-argon mixed plasma is employed for oxidizing the silicon 98, as described in “Low-Temperature Si Oxidation Using Inductively Coupled Oxygen-Argon Mixed Plasma” by M. Tabakomori et al., Jap. Jour. Appl. Phys., Part 1, Vol. 36, No. 9A (September 1997), pp. 5409-5415. In another embodiment, electron cyclotron resonance nitrous oxide plasma is employed for oxidizing the silicon 98, as described in “Oxidation of Silicon Using Electron Cyclotron Resonance Nitrous Oxide Plasma and its Application to Polycrystalline Silicon Thin Film Transistors”, J. Lee et al., Jour. Electrochem. Soc., Vol. 144, No. 9 (September 1997), pp. 3283-3287 and “Highly Reliable Polysilicon Oxide Grown by Electron Cyclotron Resonance Nitrous Oxide Plasma” by N. Lee et al., IEEE El. Dev. Lett., Vol. 18, No. 10 (October 1997), pp. 486-488.

In a step 186, a conductive material 204 is formed over the surface of the silicon 98 and in the pores 202. In some embodiments, semiconductor material 204 (FIG. 9C) is formed over the surface of the silicon 98 and in the pores 202.

Examples of materials 204 that may be used in accordance with embodiments of the invention include the materials listed in Table I above. The material 204 within the pores 202 forms the islands 26 and is chosen to have an electron affinity χ that, together with the thickness d/do and the electron affinity χ of the insulator 100 filling the gaps 28, 28′ (FIGS. 1A and 2), provides storage times in a range of from hours to days or longer, together with practical erase parameters.

In some embodiments, silicon oxycarbide is employed as the material 204 in the step 186. A process for forming thin microcrystalline films of silicon oxycarbide is described in “Transport Properties of Doped Silicon Oxycarbide Microcrystalline Films Produced by Spatial Separation Techniques” by R. Martins et al., Solar Energy Materials and Solar Cells 41/42 (1996), pp. 493-517. A diluent/reaction gas (e.g., hydrogen) is introduced directly into a region where plasma ignition takes place. The mixed gases containing the species to be deposited are introduced close to the region where the growth process takes place, which is often a substrate heater. A bias grid is located between the plasma ignition and the growth regions. spatially separating the plasma and growth regions.

Deposition parameters for producing doped microcrystalline Si_(X):C_(y):O_(z):H films may be defined by determining the hydrogen dilution rate and power density that lead to microcrystallization of the grown film 204. The power density is typically less than 150 milliWatts per cm³ for hydrogen dilution rates of 90%+, when the substrate temperature is about 250° C. and the gas flow is about 150 sccm. The composition of the films may then be varied by changing the partial pressure of oxygen during film growth to provide the desired characteristics.

In some embodiments, SiC is employed as the material 204 in the step 186. SiC films may be fabricated by chemical vapor deposition, sputtering, laser ablation, evaporation, molecular beam epitaxy or ion implantation. Vacuum annealing of silicon substrates is another method that may be used to provide SiC layers having thicknesses ranging from 20 to 30 nanometers, as described in “Localized Epitaxial Growth of Hexagonal and Cubic SiC Films on Si by Vacuum Annealing” by Luo et al., Appl. Phys. Lett. 69(7) (1996), pp. 916-918. Prior to vacuum annealing, the substrates are degreased with acetone and isopropyl alcohol in an ultrasonic bath for fifteen minutes, followed by cleaning in a solution of H₂SO₄:H₂O₂ (3:1) for fifteen minutes. A five minute rinse in deionized water then precedes etching with a 5% HF solution. The substrates are blown dry using dry nitrogen and placed in a vacuum chamber. The chamber is pumped to a base pressure of 1−2×10⁻⁶ Torr. The substrate is heated to 750 to 800° C. for half an hour to grow the microcrystalline SiC film.

In some embodiments, silicon is employed as the material 204 in the step 186. Methods for depositing high quality polycrystalline films of silicon on silicon dioxide substrates are given in “Growth of Polycrystalline Silicon at Low Temperature on Hydrogenated Microcrystalline Silicon (μc-Si:H) Seed Layer” by Parks et al., Proceedings of the 1997 MRS Spring Symposium, Vol. 467 (1997), pp. 403-408, “Novel Plasma Control Method in PECVD for Preparing Microcrystalline Silicon” by Nishimiya et al. Proceedings of the 1997 MRS Spring Symposium, Vol. 467 (1997), pp. 397-401 and “Low Temperature (450° C.) Poly-Si Thin Film Deposition on SiO₂ and Glass Usina a Microcrystalline-Si Seed Laver” by D. M. Wolfe et al., Proceedings of the 1997 MRS Spring Symposium. Vol. 472 (1997), pp. 427-432. A process providing grain sizes of about 4 nm is described in “Amorphous and Microcrystalline Silicon Deposited by Low-Power Electron-Cyclotron Resonance Plasma-Enhanced Chemical-Vapor Deposition” by J. P. Conde et al., Jap. Jour. Of Appl. Phys., Part I, Vol. 36, No. 1A (June 1997), pp. 38-49. Deposition conditions favoring small grain sizes for microcrystalline silicon include high hydrogen dilution, low temperature, low deposition pressure and low source-to-substrate separation.

In a step 188, the portion of the materials 204 deposited in the step 186 that are located on the surface of the silicon body 98 are effectively removed. In one embodiment, in the step 188, the portion of the materials 204 that are located on the surface of the silicon 98 are oxidized to provide a structure as illustrated in FIG. 9D. The step 188 proceeds until the material 204 on the surface is completely oxidized but does not proceed for long enough to oxidize all of the material 204 in the pores 202. As a result, isolated islands 26 of semiconductor material 204 surrounded by silicon dioxide 100 are formed in the pores 202 in the single crystal silicon 98 forming the body 82 of the MOSFET 80 (FIGS. 3A-C).

Significantly, the materials listed in Table I for use in the islands 26 can be oxidized to form silicon dioxide 208 or to form a volatile gas (CO₂). As a result, the islands 26 may be isolated from each other by a simple oxidation process that may not require a photolithographic step.

In a step 190, an optical gate oxide 210 (FIG. 9E) is formed on the surface of the silicon 98 and on top of the material 204 deposited in the pores 202. In a step 192, the gate oxide is patterned using conventional techniques. In a step 194, the gate 88 and backgate 88′ (FIGS. 3B and C) are formed. In one embodiment. the gate 88 and backgate 88′ are conventionally formed from polysilicon. The process 180 then ends and further fabrication is carried out using conventional processing. An advantage of the process 180 is that it does not rely on very-fine-line lithography for formation of the islands 26.

Approaches using such fine line lithography are described in “A Room-Temperature Silicon Single-Electron Metal-Oxide-Semiconductor Memory With Nanoscale Floating-Gate and Ultranarrow Channel” by L. Guo et al., Appl. Phys. Lett. 70(7) (Feb. 17, 1997), pp. 850-852 and “Fabrication And Characterization of Room Temperature Silicon Single Electron Memory” by L. Guo et al., J. Vac. Sci. Technol. B 15(6) (November/December 1997), pp. 2840-2843. These devices were fabricated using e-beam lithography and incorporate features having widths as narrow as 25 nanometers. Similarly, devices described in “Room Temperature Operation of Si Single-Electron-Memory with Self-Aligned Floating Dot Gate” (IEDM 1996), pp. 952-954, Appl. Phys. Lett. 70(13) (Mar. 31, 1997), pp. 1742-1744 and “Si Single Electron Tunneling Transistor With Nanoscale Floating Dot Stacked on a Coulomb Island by Self-Aligned Process”, Appl. Phys. Lett. 71(3) (Jul. 21, 1997), pp. 353-355, all by A. Nakajima et al., employ feature sizes as small as 30 nanometers and require much closer alignment between elements than 30 nanometers. Formation of such small feature sizes using electron beam lithography does not presently lend itself to mass production.

It will be appreciated that other techniques for forming the islands 26 (FIG. 3C) may be employed. For example, shallow implantation of relatively high doses (e.g., ca. 5-50×10¹⁴/cm²) of silicon or germanium at relatively low energies (e.g., ca. 20 keV) into relatively thin (e.g., ca. 5-20 or more nanometers) silicon dioxide layers, followed by annealing, provides nanocrystals of the implanted species that are insulated from each other and from an underlying silicon region, as described in “Fast and Long Retention-Time Nano-Crystal Memory” by H. Hanafi et al., IEEE Trans. El. Dev., Vol. 43, No. 9 (September 1996), pp. 1553-1558. Performance of memories using nanocrystals in proximity to a channel is discussed in “Single Charge and Confinement Effects in Nano-Crystal Memories” by S. Tiwari et al., Appl. Phys. Lett. 69(9) (Aug. 26, 1996), pp. 1232-1234.

FIG. 10 is a simplified block diagram of a portion of a computer system 220 including the memory MOSFET 80 of FIGS. 3A-C, in accordance with embodiments of the present invention. The computer system 220 includes a central processing unit 222 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The central processing unit 222 is coupled via a bus 224 to a memory 226, a user input interface 228, such as a keyboard or a mouse, and a display 230. The memory 226 may or may not include a memory management module (not illustrated) and does include ROM for storing instructions providing an operating system and read-write memory for temporary storage of data. The processor 222 operates on data from the memory 226 in response to input data from the user input interface 228 and displays results on the display 230. The processor 222 also stores data in the read-write portion of the memory 226. The integrated circuit 72 (FIG. 3A) is particularly useful when it is a memory integrated circuit in the read-write memory portion of the memory 226, because it may then allow the memory 226 to provide increased information storage capacity and/or density.

The embodiments of the present invention provide a compact, sensitive memory cell and permit very high storage capacity memories to be fabricated. Additionally, the inventive memory cell does not require high resolution lithography for fabrication of the islands that store charge.

It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. Therefore, the present invention is to be limited only by the appended claims. 

What is claimed is:
 1. A memory integrated circuit comprising: row and column driving and addressing circuitry; a first memory array including a first plurality of memory cells formed from p-type silicon and arranged in rows and columns, the first plurality of memory cells having a first latency, the first memory array coupled to the driving circuitry and the addressing circuitry; and a second memory array including a second plurality of memory cells formed from p-type silicon and arranged in rows and columns, the second plurality of memory cells having a second latency greater than the first latency, the second memory array coupled to the driving and the addressing circuitry, wherein the memory cells in the first and second pluralities of memory cells each include a MOSFET comprising: a source coupled to a first end of a channel of semiconductor material; a drain coupled to a second end of the channel; a gate formed on a gate insulator on the channel, the gate and the gate insulator extending from the source to the drain; and one or more islands of conductive material each surrounded by an insulator, each island and surrounding insulator formed in a pore extending into the channel.
 2. The memory integrated circuit of claim 1 wherein the first latency is less than one second and the second latency is greater than a week.
 3. The memory integrated circuit of claim 1 wherein semiconductor material comprising each cell of the first and second pluralities of memory cells has a maximum dimension of less than two microns.
 4. The memory integrated circuit of claim 1 wherein the first plurality of memory cells incorporate a surrounding insulator having a first thickness and the second plurality of memory cells incorporate a surrounding insulator having a second thickness different than the first thickness.
 5. The memory integrated circuit of claim 4 wherein the first and second pluralities of memory cells incorporate surrounding insulators comprising silicon dioxide.
 6. The memory integrated circuit of claim 1 wherein the first plurality of memory cells incorporate islands comprising a first material and the second plurality of memory cells incorporate islands comprising a second material having a work function different than the first material.
 7. The memory integrated circuit of claim 1 wherein the semiconductor material comprises p-type silicon having a carrier concentration of 10⁻¹⁵/cm³ or less.
 8. A memory integrated circuit comprising: row and column driving and addressing circuitry; a first memory array coupled to the driving and addressing circuitry and having a first plurality of memory cells with first data retention characteristics, the memory cells having a gate and an insulator formed over a channel region of semiconductive material, the channel region having at least one island of conductive material surrounded by an insulator extending into a pore formed in the channel region; and a second memory array coupled to the driving and addressing circuitry and having a second plurality of memory cells with second data retention characteristics different than the first data retention characteristics.
 9. The memory integrated circuit of claim 8, further comprising a backgate electrode formed near the channel and separate from the gate and formed from a polysilicon material.
 10. The memory integrated circuit of claim 8 wherein the memory cells in the first and second pluralities of memory cells each include a MOSFET comprising: a source coupled to a first end of the channel; and a drain coupled to a second end of the channel, wherein the gate and the gate insulator extending from the source to the drain.
 11. The memory integrated circuit of claim 8 wherein the first plurality of memory cells incorporate a surrounding insulator having a first thickness and the second plurality of memory cells incorporate a surrounding insulator having a second thickness different than the first thickness.
 12. The memory integrated circuit of claim 11 wherein the first and second pluralities of memory cells incorporate surrounding insulators comprising silicon dioxide.
 13. The memory integrated circuit of claim 8 wherein the first plurality of memory cells incorporate islands comprising a first material and the second plurality of memory cells incorporate islands comprising a second material having a work function different than the first material.
 14. The memory integrated circuit of claim 8 wherein the semiconductor material comprises p-type silicon having a carrier concentration of 10³¹ ¹⁵/cm³ or less.
 15. The memory integrated circuit of claim 8 wherein the memory cells of the second memory array comprises a gate and an insulator formed over a channel region of semiconductive material, the channel region having at least one island of conductive material surrounded by an insulator extending into a pore formed in the channel region. 